Overview. Design greater bandwidth and feature-rich network equipment with Microsemi's 10 Gigabit Ethernet (GE) physical layer (PHY) transceiver ICs. Microsemi's 10GE PHY portfolio is highly flexible, covering a broad range of port speeds and interface types. Microsemi's latest generation 10GE PHYs feature VeriTime™, Microsemi's patent pending timing technology delivering the industry's de facto most accurate IEEE 1588 timing for IP Edge networks.
DS813 October 19, 2011 www.xilinx.com 3 Product Specification LogiCORE IP 10-Gigabit Ethernet MAC v11.2 The 10-Gigabit Ethernet MAC core is designed to be attached to the Xilinx IP XAUI core, the Xilinx IP RXAUI core ,
You get information about the 10GBase-T PHY from datasheets provided by the 10GBase-T PHY manufacturer. Hint: this isn't Xilinx. You haven't stated which PHY you are using. Perhaps you want to keep it confidential, or perhaps you don't know yet. If the latter, I suggest contacting one of the PHY manufacturers such as Aquantia or Broadcom. You ...
Product Updates. External PHY 2-Port SFP+ FMC Module (Vita57.1) Vita 57 provides a mechanical standard for I/O mezzanine modules. This standard introduces a methodology that shall allow the front panel IO of IEEE 1101 form factor cards to be configured via mezzanine boards.
Xilinx, Texas Instruments team on energy-efficient 5G radio chips. By combining Xilinx's Zynq UltraScale+ MPSoC family and adaptable RF IP with the AFE7769 quad-channel RF transceiver from TI, device developers will be better able address the opex and capex concerns of large operators and private networks.
Towards external PHY tx_serial_clk Towards external PHY 644.53125 MHz/322.265625 MHz 5.15625 GHz rx_clkout tx_clkout Note: 1. To configure the IP between 10G and 25G, follow the reconfiguration sequence as defined in the Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide and Intel Stratix 10 E-Tile Transceiver PHY User Guide.
Xilinx offers a vast portfolio of Ethernet IP cores including the 1G and 10G Ethernet MAC, and 1G and 10G Ethernet PCS/PMA. The Ethernet MA C has an AXI4-Stream compliant user interface The 1G/10G Ethernet PHY Intel ® FPGA intellectual property (IP) core supports functionality of both the standard physical coding sublayer (PCS) and the higher ...
The 10-Gigabit Ethernet MAC core is designed to be attached to the Xilinx IP XAUI core , the Xilinx IP RXAUI core, and the Xilinx IP 10G Ethernet PCS/PMA. Figure 1-4 illustrates the 10-Gigabit Ethernet MAC and XAUI cores in a system using an XPAK optical module. See Interfacing to the Xilinx XAUI IP Core, page 79 for details on using the two cores